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CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 1 general description features ? patent filed #5,565,761, #5,747,977, #5,742,151, #5,804,950, #5,798,635 ? pfc has the green mode to meet blue angel and energy star spec. ? 8-pin soic package ? use rac as the startup resistor which can be > 2000k or higher at iac pin ? it can use the hv bipolar to start up the chip and it helps green mode. ? easy to configure into boost follower ? enable lowest bom for power supply with pfc ? patented slew rate enhanced voltage error amplifier with advanced input current shaping technique ? universal line input voltage ? ccm boost or dcm boost with leading edge modulation pfc using input current shaping technique ? feedforward iac pin to do the automatic slope compensation ? pfcovp, vccovp, precisio n -1v pfc ilimit, pfc pfc on-off detect comparator to meet ul1950 ? low supply currents; start- up: 100ua typical, operating current: 2ma typical. ? uvlo, refok, and brownout protection the CM6510C is the green-mode pfc controller for high density ac adapter. for the power supply less than 200watt, it?s input current s haping pfc performance could be very close to the performance of the cm6800 or ml4800 leading edge modulation average current topology. CM6510C offers the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching fets, and results in a power supply fully compliant to iec1000-3-2 specifications. the CM6510C includes circuits for the impl ementation of a leading edge, input current shaping technique ?boost? type pfc. the CM6510C?s pfc operate at the same frequency, 67.5khz. a pfc ovp comparat or shuts down the pfc section in the event of a s udden decrease in load. the pfc section also includes peak current limiting for enhanced system reliability. pfc has the green mode functions. when the load is below gmth, green mode threshold, pfcout is turned off. the gmth can be programmed by the designer. applications pin configuration ? ac adaptor ? open frame 8 pin sop (s08) top view vcc pfc on-off 3 vfb gnd veao 6 pfc out 8 2 iac 5 4 isense 1 7 www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 2 pin description operating voltage pin no. symbol description min. typ. max. unit 1 gnd ground 2 iac feedforward input to do slope compensation and to start up the system. during the start up, iac is connected to vcc until vcc is greater than 13v. 0 1 v 3 i sense current sense input to the pfc cu rrent limit comparator -5 0.7 v 4 veao pfc transconduct ance voltage error ampl ifier output 0 6 v 5 v fb pfc transconductance voltage e rror amplifier input 0 2.5 3 v 6 pfc on-off it can turn off pfc stage when it is below (vcc-1.4v)/2. 0 vcc v 7 vcc positive supply 10 18 v 8 pfc out pfc driver output 0 vcc v ordering information initial accuracy (khz) part number operation frequency min typ max temperature range package CM6510Cxis* fpwm = fpfc = 67.5khz 60 67 74 -40 to 125 8 pin sop(s08) note: 1. x : suffix for halogen free and pb free product 2. initial accuracy : t a =25 www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 3 block diagram vcc uvlo .. gnd 16.4v . . greenmode pfc ovp + - . - + - 17.9v pfc ilimit s r q q r -1v vrefdk + - . (vcc-1.4v)/2 v to ramp iac 2 uvb 0.5v pfcclk . uvb vfb 5 isense 3 2.5v fpfc=67.5khz r1b . 2 1 r1c . 2 1 iac + - . vcc ovp + - . - - + . gmv + - .veao 4 .. pfc cmp 2.5v v=17ua + - . 2.75v pfc on-off 6 pfcout 8 r1a . 2 1 vcc 7 gnd fault gnd 1 brokenwire pfc clk protected by patent vcc absolute maximum ratings absolute maximum ratings are those values beyo nd which the device could be permanently damaged. parameter min. max. units v cc max 20 v iac (before start up) gnd-0.3 vcc + 0.3 v iac (after start up) gnd-0.3 1.0 v i sense voltage -5 0.7 v pfc out gnd ? 0.3 vcc + 0.3 v veao 0 6.3 v voltage on any other pi n gnd-0.3 vcc + 0.3 v peak pfc out current, source or sink 0.5 a pfc out energy per cycle 1.5 j junction temperature 150 storage temperature range -65 150 operating temperature range -40 125 lead temperature (soldering, 10 sec) 260 thermal resistance ( ja ) 80 /w www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 4 electrical characteristics unless otherwise stated, these sp ecifications apply vcc=+14v, t a =operating temperature range (note 1) CM6510C symbol parameter test conditions min. typ. max. unit voltage error amplifier (g mv ) input voltage range 0 5 v transconductance v noninv = v inv , veao = 3.75v 30 65 90 mho feedback reference voltage 2.43 2.5 2.56 v input bias current note 2 -0.5 -1.0 a output high voltage 5.8 6.0 v output low voltage 0.1 0.4 v sink current v fb = 3v, veao = 6v -35 -20 a source current v fb = 1.5v, veao = 1.5v 30 40 a open loop gain 50 60 db power supply rejection ratio 11v < v cc < 16.5v 50 60 db iac input impedance isense = 0v, t a =25 35 40 45 k vcc ovp comparator threshold voltage 17.3 17.9 18.5 v hysteresis 1.3 1.5 1.75 v pfc ovp comparator threshold voltage 2.64 2.77 2.85 v hysteresis 230 300 mv pfc i limit comparator threshold voltage -1.1 -1 -0.9 v delay to output 150 300 ns v in ok comparator threshold voltage 2.30 2.45 2.55 v hysteresis 1.65 1.75 1.85 v pfc on-off detect comparator fault detect high 2.70 2.77 2.85 v time to fault detect high v fb =v fault detect low to v fb = open, 470pf from v fb to gnd 2 4 ms fault detect low 0.4 0.5 0.6 v www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 5 electrical characteristics (conti.)unless otherwise stated, th ese specifications apply vcc=+14v, t a =operating temperature range (note 1) CM6510C symbol parameter test conditions min. typ. max. unit oscillator voltage stability 10v < v cc < 15v 1 % temperature stability 2 % total variation line, temp 60 67 74.5 khz pfc dead time (note 2) 0.3 0.45 0.65 us pfc minimum duty cycle i ac =100ua,v fb =2.55v, i sense = 0v 1 % maximum duty cycle i ac =0ua,v fb =2.0v, i sense = 0v 90 95 % output low rdson 15 22.5 ohm i out = -100ma 0.8 1.5 v output low voltage i out = -10ma, v cc = 8v 0.4 0.8 v output high rdson 30 45 ohm output high voltage i out = 100ma, v cc = 15v 13.5 14.2 v rise/fall time (note 2) c l = 1000pf 50 ns supply start-up current v cc = 11v, c l = 0 100 150 ua operating current v cc = 15v, c l = 0 2 4.0 ma undervoltage lockout th reshold 12.35 13 13.65 v undervoltage lockout hy steresis 2.7 3 3.3 v note 1: limits are guaranteed by 100% testing, sampli ng, or correlation with worst-case test conditions. note 2: guaranteed by design, not 100% production test. www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 6 typical performanc e characteristic 57 64 71 78 85 92 99 106 113 120 127 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 vfb (v) transconductance (umho) voltage error amplifier (g mv ) transconductance www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 7 functional description the CM6510C consists of an icst (input current shaping technique), ccm (continuous conduction mode) or dcm (discontinuous conduction mode) boost pfc (power factor correction) front end and a synchronized pwm (pulse width modulator) back end. the CM6510C is designed to replace fan6803 (8 pin sop package), which is the second generation of t he ml4803 with 8 pin package. it is distinguished from earlier combo controllers by its low count, innovative input current shaping technique, and very low start-up and operating cu rrents. it uses conventional trailing-edge modulation, while the pfc uses leading-edge modulation. this patented leading edge/trailing edge (lete) modulation technique helps to minimize ripple current in the pfc dc buss capacitor. the main improvements from ml4803 are: 1. add green mode functions for pfc 2. remove the one pin error amplifier and add back the slew rate enhancement gmv, which is using voltage input instead of current input. this transconductance amplifier will increase the transient response 5 to 10 times from the conventional op 3. vfb pfc ovp comparator 4. pfc pfc on-off detect for ul1950 compliance and enhanced safety 5. a feedforward signal from iac pin is added to do the automatic slope compensati on. this increases the signal to noise ratio during the light load; therefore, thd is improved at light load and high input line voltage. 6. CM6510C does not require the bleed resistor and it uses the more than 800k ohm resistor between iac pin and rectified line voltage to feed the initial current before the chip wakes up. 7. a 10ms digital pwm soft start circuit is added 8. 10 pin sop package 9. no internal zener but with vccovp comparator the CM6510C operates pfc sections at 67khz. several protection features have been built into the CM6510C. these include soft-start, redundant pfc overvoltage protection, pfc pfc on-off detect, vinok, peak current limiting, duty cy cle limiting, under-voltage lockout, reference ok comparator and vccovp. detailed pin descriptions iac (pin 2) typically, it has a feedforward resistor, rac, 2kk~10kk ohm resistor connected between this pin and rectified line input voltage. this pin serves 2 purposes: 1.) during the startup condit ion, it supplies the startup current; therefore, the system does not requires additional bleed resistor to start up the chip. 2.) the current of rac wi ll program the automatic slope compensation for the system. this feedforward signal can increase the signal to noise ratio for the light load condition or the high input line voltage condition. optional resistor between iac and vcc: this resistor is about 100k ohm, it can improve the thd of the input current at high line and light load isense (pin 3) this pin ties to a resistor which senses the pfc input current. this signal should be negative with respect to the ic ground. it internally feeds the pulse-by-pulse current limit comparator and the current sense feedback signal. the ilimit trip level is ?1v. the isense feedback is internally multiplied by a gain of four and compared against the internal programmed ramp to set the pfc duty cycle. the intersection of the boost inductor current downslope with the internal programming ramp de termines the boost off-time. it requires a rc filter between isense and pfc boost sensing resistor. veao (pin 4) this is the pfc slew rate enhanced transconductance amplifier output which needs to connected with a compensation net work ground. vfb (pin 5) besides this is the pfc slew rate enhanced transconductance input, it also tie to a couple of protection comparators, pfcovp, and pfc pfc on-off detect pfc on-off (pin 6) current information, the optocouple goes into pfc on-off pin. therefore, it is the sum amplifier input. soft start can be triggered by the following conditions: 1.) during the startup (vcc is less than 10v) 2.) dc to dc short (pfc on-off is greater thanvcc-0.7v) www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 8 vcc (pin 7) vcc is the power input connection to the ic. the vcc start-up current is 100ua. the no-load icc current is 2ma. vcc quiescent current will include both the ic biasing currents and the pfc output current. given the operating frequency and the mosfet gat e charge (qg), average pfc and pwm output currents can be calculated as iout = qg x f. the average magnetizing current required for any gate drive transformers must also be included. the vcc pin is also assumed to be proportional to the pfc output voltage. internally it is tied to the vcc ovp comparator (17.9v) providing redundant high-speed over-voltage protection (ovp) of the pfc st age. vcc also ties internally to the uvlo circuitry and vrefok comparator, enabling the ic at 13v and disabling it at 10v. vcc must be bypassed with a high quality ceramic bypass capacitor placed as close as possible to the ic. good bypassing is critical to the proper o peration of the CM6510C. vcc is typically produced by an additional winding off the boost inductor or pfc choke, providing a voltage that is proportional to the pfc output voltage. since the vcc ovp max voltage is 17.9v, an internal shunt limits vcc overvoltage to an acceptable value. an external clamp, such as shown in figure 1, is desirable but not necessary. vcc gnd 1n5250b figure 1. optional vcc clamp this limits the maximum vcc that can be applied to the ic while allowing a vcc which is high enough to trip the vcc ovp. an rc filter at vcc is required between boost trap winding and vcc. pfcout (pin 8) pfc out is the high-current power driver capable of directly driving the gate of a power mosf et with peak currents up to -1a and +0.5a. both outputs are actively held low when vcc is below the uvlo threshold level which is 15v or vrefok comparator is low. power factor correction power factor correction makes a nonlinear load look like a resistive load to the ac line. for a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). a common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacit ive input filter fed from the line. the peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). if the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the ac line and a unity power factor will be achieved. to hold the input current draw of a device drawing power from the ac line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. the pfc secti on of the CM6510C uses a boost-mode dc-dc converter to accomplish this. the input to the converter is the full wave rectified ac line voltage. no bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the ac input and back to zero. by forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current draws from the power line matches the instantaneous line voltage. one of these conditions is t hat the output voltage of the boost converter must be set higher than the peak value of the line voltage. a commonly used value is 385vfb, to allow for a high line of 270vac rms . the other condition is that the current that the converter is allo wed to draw from the line at any given instant must be proportional to the line voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 9 pfc control: leading edge modulation with input current shaping technique (i.c.s.t.) the only differences between the conventional pfc control topology and i.c.s.t. is: the current loop of the convent ional control method is a close loop method and it requires a detail understanding about the system loop gain to design. with i.c.s.t., since the current loop is an open loop, it is very straightforward to implement it. the end result of the any pfc system, the power supply is like a pure resistor at low frequenc y. therefore, current is in phase with voltage. in the conventional control, it forces the input current to follow the input voltage. in CM6510C, the chip thinks if a boost converter needs to behave like a low frequency resistor, what the duty cycle should be. the following equations is CM6510C try to achieve: in in e i v r = (1) in l i i = (2) equation 2 means: average boost inductor current equals to input current. d out l in i v i v (3) therefore, input instantaneous power is about to equal to the output instant aneous power. for steady state and for the each phase angle, boost converter dc equation at continuous conduction mode is: ) 1 ( 1 d v v in out ? = (4) rearrange above equations, (1), (2),(3), and (4) in term of vout and d, boost converter duty cycle and we can get average boost diode current equation (5): e out d r v d i ? = 2 ) 1 ( (5) also, the average diode current can be expressed as: dt t i t i off t d sw d ? = ) ( 1 0 (6) if the value of the boost inductor is large enough, we can assume d d i t i ~ ) ( . it means during each cycle or we can say during the sampling, the diode current is a constant. therefore, equation (6) becomes: ) 1 ( ' d i d i t t i i d d sw off d d ? = = = (7) combine equation (7) and equation (5), and we get: sw off e out d e out d e out d t t r v i r v d i r v d d i = = = ' 2 ' ' ) ( (8) from this simple equation (8), we implement the pfc control section of the CM6510C. leading/trailing modulation conventional pulse width modulation techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the syst em clock. the error amplifier output is then compared with the modulating ramp. when the modulating ramp reaches the le vel of the error amplifier output voltage, the switch will be turned off. when the switch is on, the inductor current will ramp up. the effective duty cycle of the trailing e dge modulation is determined during the on time of the switch. figure 2 shows a typical trailing edge control scheme. in case of leading edge modula tion, the switch is turned off right at the leading edge of the system clock. when the modulating ramp reaches the le vel of the error amplifier output voltage, the switch w ill be turned on. the effective duty-cycle of the leading edge modulation is determined during off time of the switch. figure 3 shows a leading edge control scheme. www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 10 one of the advantages of this control technique is that it required only one system clock. switch 1(sw1) turns off and switch 2 (sw2) turns on at the same instant to minimize the momentary ?no-load? period, thus lowering ripple voltage generated by the switching action. with such synchronized switching, the ri pple voltage of the first stage is reduced. calculation and ev aluation have shown that the 120hz component of the pfc?s output ripple voltage can be reduced by as much as 30% using this method, substantially reducing dissipa tion in the high-voltage pfc capacitor. typical applications pfc section: pfc voltage loop error amp, veao the ml4803 utilizes an one pin voltage error amplifier in the pfc section (veao). in the CM6510C, it is using the slew rate enhanced transconductance amplifier, which is the same as error amplifie r in the cm6800. the unique transconductance profile can speed up the conventional transient response by 10 times. the internal reference of the veao is 2.5v. the input of the veao is vfb pin. pfc voltage loop compensation the voltage-loop bandwidth must be set to less than 120hz to limit the amount of line cu rrent harmonic distortion. a typical crossover frequency is 30hz. the voltage loop gain (s) cv v dc eao 2 outdc in fb eao out fb eao out z * gm * c * s * v * v v 5 . 2 * p v v * v v * v v = z cv : compensation net work for the voltage loop gm v : transconductance of veao p in : average pfc input power v outdc : pfc boost output voltage; typical designed value is 380v. c dc : pfc boost output capacitor v eao : this is the necessary c hange of the veao to deliver the designed average input power. the average value is 6v-3v=3v since when the input line voltage increases, the delta veao will be reduced to de liver the same to the output. to over compensate, we choose the delta veao is 3v. internal voltage ramp the internal ramp current source is programmed by way of veao pin voltage. when veao increases the ramp current source is also increase. this current source is used to develop the internal ramp by c harging the internal 30pf +12/ -10% capacitor. the frequency of the internal programming ramp is set inter nally to 67khz. design pfc isense filtering isense filter, the rc filter between rs and isense: there are 2 purposes to ad d a filter at isense pin: 1.) protection: during start up or inrush current conditions, it will have a large voltage cross rs, which is the sensing resistor of the pfc boost converter. it requires the isense filter to attenuate the energy. 2.) reduce l, the boost induc tor: the isense filter also can reduce the boost inductor value since the isense filter behaves lik e an integrator before going isense which is the input of the current error amplifier, ieao. www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 11 the i sense filter is a rc filter. the resistor value of the i sense filter is between 100 ohm and 50 ohm. by selecting r filter equal to 50 ohm will keep the offset of the ieao less than 5mv. usually, we design the pole of i sense filter at fpfc/6, one sixth of the pfc sw itching frequency. therefore, the boost inductor can be reduced 6 times without disturbing the stability. theref ore, the capacitor of the i sense filter, c filter , will be around 283nf. iac, r ac , automatic slope compensation, dcm at high line and light load, and startup current there are 4 purposes for iac pin: 1.) for the leading edge mo dulation, when the duty cycle is less than 50%, it requires the similar slope compensation, as the duty cycle of the trailing edge modulation is greater than 50%. in the CM6510C, it is a relatively easy thing to design. use an more than 2kk ohm resistor, r ac to connect iac pin and the rectified line voltage. it will do the automatic sl ope compensation. if the input boost inductor is too small, the r ac may need to be reduced more. 2.) during the startup perio d, rac also provides the initial startup current, 100ua;therefore, the bleed resistor is not needed. 3.) since iac pin with r ac behaves as a feedforward signal, it also enhances the signal to noise ratio and the thd of the input current. 4.) it also will try to keep the maximum input power to be constant. however, the maximum input power will still go up when the input line voltage goes up. start up of the system, uvlo, vrefok and soft start during the start-up period, r ac resistor will provide the start up current~100ua from the rectif ied line voltage to iac pin. inside of CM6510C during the start-up period, iac is connected to vcc until the vcc reaches uvlo voltage which is 13v (uvb) and internal reference voltage is stable, it will disconnect itself from vcc. during the start up, the soft start function is triggered and the duration of the soft start will last around 10ms. pfc section wakes up after start up period after start up period, pfc section will softly start since veao is zero before the star t-up period. since veao is a slew rate enhanced transconductance amplifier (see figure 3), veao has a high impedance output like a current source and it will slowly charge the compensation net work which needs to be designed by using the voltage loop gain equation. before pfc boost output reaches its design voltage, it is around 380v and vf b reaches 2.5v, pwm section is off. pfc ovp comparator pfc ovp comparator sense vfb pin which is the same the voltage loop input. the good thing is the compensation network is connected to veao. the pfc ovp function is a relative fast ovp. it is not lik e the conventional error amplifier which is an operational amplifier and it requires a local feedback and it make the ovp action becomes very slow. the threshold of the pfc ovp is 2.5v+10% =2.75v with 250mv hysteresis. pfc on-off detect comparator to improve power supply reliability, reduce system component count, and simplify compliance to ul1950 safety standards, the CM6510C includes pfc on-off detect. this feature monitors vfb (pin 5) fo r certain pfc fault conditions. in case of a feedback path failure, the output of the pfc could go out of safe operating limit s. with such a failure, vfb will go outside of its normal operating area. should vfb go too low, too high, or open, pfc on-off detect senses the error and terminates the pfc output drive. pfc on-off detect is an entirely internal circuit. it requires no external components to serve its protective function. vcc ovp and generate vcc for the CM6510C system, if vcc is generated from a source that is proportional to the pf c output voltage and once that source reaches 17.9v, pfcout , pfc driver will be off. the vcc ovp resets once the vcc discharges below 16.4v, pfc output driver is enabled. it serves as redundant pfc ovp function. typically, there is a bootstra p winding off the boost inductor. the vcc ovp comparator senses when this voltage exceeds 17.9v, and terminates the pfc output drive. once the vcc rail has decreased to below 16.4v the pfc output drive be enabled. given that 16v on vcc corresponds to 380v on the pfc output, 17.9v on vcc corresponds to an ovp level of 460v. it is a necessary to put rc filter between bootstrap winding and vcc. for vcc=15v, it is sufficient to drive either a power mosfet or a igbt. www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 12 uvlo the uvlo threshold is 13v providing 3v hysteresis. pfcout pfcout is cmos drivers. it has adaptive anti-shoot through to reduce the switching loss. its pull-up is a 30ohm pmos driver and its pull-down is a 15ohm nmos driver. it can source 0.5a and sink 1a if the vcc is above 15v. pfc on-off when pfc on-off is less than (v cc-1.4v)/2, CM6510C will turn off pfc. usually; it means load has been reduced to a level, which is the level of the green mode threshold. usually, we set the green mode threshold around 20% of the full load. after turning off pfc, the efficiency will be increased due to the input voltage is higher and less switching events. component reduction components associated with the vrms and ieao pins of a typical pfc controller such as the cm6800 have been eliminated. the pfc power limit and bandwidth does vary with line voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 13 application circuit 100k in5406 1m ac inlet l fg n 1n5406 380vdc 380vdc 470pf/250v 1n4148 2m 13k 102pf vcc 684pf 10 10m 110k 0.47uf/400v gnd 0.08 2w(s) + 1uf 1m 10k er806 47 + 180uf/450v in5406 1n4148 473pf 2m 1n4148 330k vcc 12v 10 1/2w t106-75 CM6510C 3 2 4 5 6 7 8 1 pfc on-off iac ve ao vfb v+i vcc pfc out gnd 102pf emi 104pf 15v - + gbl408 14n50 10k 474pf www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 14 package dimension 8-pin sop (s08) www.datasheet.co.kr datasheet pdf - http://www..net/
CM6510C 8-pin g reen m ode pfc controller 2009/07/15 rev1.0 ch ampion microelectronic co rporation page 15 important notice champion microelectronic corporation (cmc) reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its custom ers to obtain the latest version of relevant information to ve rify, before placing orders, that the information being relied on is current. a few applications using integrated circuit products may involv e potential risks of death, personal injury, or severe property or environmental damage. cmc integrated circ uit products are not designed, intended, au thorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. use of cmc products in such applications is understood to be fully at the risk of the cust omer. in order to minimize risks associated with the customer?s applications, th e customer should provide adequate design and operating safeguards. hsinchu headquarter sales & marketing 5f, no. 11, park avenue ii, science-based industrial park, hsinchu city, taiwan 21f., no. 96, sec. 1, sintai 5th rd., sijhih city, taipei county 22102, taiwan, r.o.c. t e l : +886-3-567 9979 t e l : +886-2-2696 3558 f a x : +886-3-567 9909 f a x : +886-2-2696 3559 http://www.champion-micro.com www.datasheet.co.kr datasheet pdf - http://www..net/

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